1. Field of the Invention
The present invention relates generally to a semiconductor structure. More particularly, the present invention relates to an improved semiconductor memory device capable of suppressing wordline-wordline (WL-WL) disturb and/or bitline-bitline (BL-BL) coupling during the operation of the memory device. A method of making the semiconductor structure is also disclosed.
2. Description of the Prior Art
Memory cell layouts are constantly miniaturized to be in accordance with product demands and the trends of high integration, high performance, and low power consumption.
One conventional dynamic random access memory (DRAM) layout includes wordlines that are perpendicular to the bitlines. Two wordlines may pass a same active area for forming two transistors in the same active area. The lengthwise direction of the active area may intersect with the wordlines at an acute angle. A bitline contact plug is located between the two transistors and electrically connected to a bitline. The bitline is electrically coupled to a source doping region that is commonly shared by the two transistors.
However, the above-described DRAM configuration suffers from so-called wordline-wordline (WL-WL) disturb failures when the operation state of one of the adjacent cells changes the state of information stored in the other of the adjacent cells. In the field of DRAM technology, there is a need for an improved semiconductor structure that is capable of reducing the WL-WL disturb failures.